The invention relates to integrated circuits, and more particularly, to band edge engineered Vt offset devices, design structures for band edge engineered Vt offset devices and methods of fabricating such structures.
CMOS processing requires both NMOS and PMOS devices. In these devices, high-k/metal gate implementation requires a metal that works for NMOS (typically of workfunction between 4.2 eV and 4.6 eV) and a metal that works for PMOS (typically of workfunction between 4.8 eV and 5.2 eV). This constitutes the material requirements of two “work function” metals (properties capable of achieving Vt), one needed for each device. The work function metals between 4.2 eV to 4.6 eV and 4.8 to 5.2 eV are needed to adjust the Vt of the NMOS and PMOS devices, respectively.
In conventional processing of CMOS, a single metal is used in the gate fabrication of the NMOS and another single metal is used for the gate fabrication of the PMOS. Also, it is known that most metals with high work function have stable bulk characteristics after high thermal processing. However, these metals alter their interface characteristics with the high-k dielectric after high-temperature processing which manifests itself as Vt variation and dielectric leakage. These conditions lead to decreased device reliability.
Devices with workfunctions nearer to the silicon midgap energy require lower values of channel doping in order to achieve proper Vt. This to leads to difficulties in controlling Vt roll-off, that is, the rapid change in Vt with variation in gate length, thereby leading to Vt tolerance degradation, which is especially detrimental to analog circuits.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.